Clock Generator Module:
Port Description: CLKIN is the external input clock. If it is an external differential clock signal, specify the *_p and *_n pins on the PORT line of the MHS file to be the same Net, such as dcm_clk_s, and specify the positive and negative differential polarities respectively. CLKFBIN is the CLKFB input port of DCM. If it is selected, the DCM uses external feedback mode. At this time, the CLKFBOUT output port should also be used, and CLKFBOUT is connected to the CLK0 output port, and CLKFBIN is connected to the signal after CLKFBOUT passes through the clock distribution network. Adjust the clock signal delay. If CLKFBIN is not used, CLKFBOUT is not used. After the output of CLK0 is buffered by BUFG in DCM, it is sent to CLK0 port and sent to CLKFBIN all the way.
Parameter Description:
C_CLKFBIN_FREQ, C_CLKFBOUT_FREQ set the frequency of CLKFBIN and CLKFBOUT respectively, setting 0 means not to use, the two must be set the same. C_CLKOUTI_FREQ sets the output frequency of CLKOUTI, and 0 means that CLKOUTI is not used. C_CLKOUTI_GROUP is used to set the group number. Multiple outputs can be set to the same group, so that the same group clock is output through the same DCM or PLL, reducing the phase skew between clocks. If C_CLKOUTi_BUF is set to TRUE, the corresponding CLKOUTi is inserted into BUFG, which is generally set to TRUE, but the clock signal output to some DDR particles is not set to TRUE.
Processor System Reset Module:
Port Description: Slowest_sync_clk is the slowest clock in the system, generally the PLB bus clock. Ext_Reset_In is an external input reset signal, and Aux_Reset_In is an auxiliary second external input reset signal, which is generally not used. MB_Debug_Sys_Rst is used for debugging and has the same function as Ext_Reset_In, but it is always active. Dcm_locked is the module input signal. If the system does not use DCM, it is connected high. If a DCM is used to generate the system clock, the Locked signal of this DCM is connected. If the system uses multiple DCMs to generate the system clock, the last Locked DCM is connected. MB_Reset is the reset signal of the output MB. Bus_Struct_Reset and Peripheral_Reset are the bus and peripheral reset signals of the output, and the number can be customized according to C_NUM_BUS_RST and C_NUM_PERP_RST.
Note: The DCM's Locked signal is high and all output clocks are stable.
Parameter description: C_EXT_RST_WIDTH, C_AUX_RST_WIDTH defines the width of the external input reset signal (port Ext_Reset_In). Slowest_sync_clk is the PLB bus clock, Ext_Reset_In is the clock period set by C_EXT_RST_WIDTH plus 1 to 2 cycles (taking into account the clock delay in the circuit). When Ext_Reset_In becomes 0, the circuit exits the reset state after C_EXT_RST_WIDTH cycles.
C_EXT_RESET_HIGH, C_AUX_RESET_HIGH defines whether the external input reset signal is active high or low. Generally set high effective, that is 1. MB_Debug_Sys_Rst is always active high.
C_NUM_BUS_RST, C_NUM_PERP_RST defines the number of reset signals required by the bus and peripherals. If there is one PLB bus and two OPB buses, C_NUM_BUS_RST can be set to 3. In some cases, it may be beneficial to drive and route. Generally, it can be 1, and the three buses can be driven by the same bus reset signal. C_NUM_PERP_RST is similar.
Control mode: The reset pulse sequence is automatically generated when the power is turned on; when the external Ext_Reset_In and Aux_Reset_In meet the reset condition, the module generates a reset pulse sequence; when the MB_Debug_Sys_Rst meets the reset condition, the module generates a reset pulse sequence.
Article source: column of seadoncas
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