In the design of the PCB board, the anti-ESD design of the PCB can be realized by layering, proper layout and installation. By adjusting the PCB layout and wiring, ESD can be well protected. Multilayer PCBs can be used as much as possible. Compared to double-sided PCBs, ground planes and power planes, as well as closely spaced signal line-ground spacing can reduce common mode impedance. It is inductively coupled to 1/10 to 1/100 of a double-sided PCB. It has components for the top and bottom surfaces and has a short connecting line.
Static electricity from inside the human body, the environment, and even electronic equipment can cause various damage to delicate semiconductor chips, such as penetrating a thin insulating layer inside the component; damaging the gates of MOSFETs and CMOS components; and flip-flops in CMOS devices Short-circuited, reverse-biased PN junction; short-circuited forward-biased PN junction; melted weld line or aluminum wire inside the active device. In order to eliminate the interference and destruction of electronic devices by electrostatic discharge (ESD), various technical means are needed to prevent them.
In the design of the PCB board, the anti-ESD design of the PCB can be realized by layering, proper layout and installation. In the design process, most of the design modifications can be limited to increasing or decreasing components through prediction. ESD can be well protected by adjusting the PCB layout. Here are some common precautions.
When using a multi-layer PCB as much as possible, the ground plane and power plane, as well as the closely spaced signal line-ground spacing, can reduce common mode impedance and inductive coupling relative to a double-sided PCB, enabling it to reach 1/2 of a double-sided PCB. 10 to 1/100. Try to keep each signal layer close to a power or ground plane. For high-density PCBs with components on the top and bottom surfaces, short traces, and many fill locations, consider using inner traces.
For double-sided PCBs, tightly interleaved power and ground grids are used. The power cord is close to the ground, and should be connected as much as possible between the vertical and horizontal lines or the fill area. The grid size on one side is less than or equal to 60 mm. If possible, the grid size should be less than 13 mm. Make sure that each circuit is as compact as possible.
Keep all connectors aside as much as possible.
If possible, route the power cord from the center of the card away from areas that are susceptible to direct ESD.
Place a wide chassis ground or polygon fill on all PCB layers underneath the connector (which is easily hit directly by the ESD) and connect them with vias every 13mm.
A mounting hole is placed on the edge of the card, and the top and bottom pads of the solderless solder are attached to the chassis ground.
When assembling the PCB, do not apply any solder to the top or bottom pads. Use a screw with an inset washer to make the PCB in close contact with the metal chassis/shield or ground plane bracket.
Between the chassis ground and circuit ground of each layer, the same "isolation zone" should be set; if possible, keep the separation distance 0.64mm. At the top and bottom of the card close to the mounting hole, every 100mm along the chassis The wires connect the chassis ground and the circuit ground with a 1.27 mm wide wire. Adjacent to these connection points, pads or mounting holes for mounting are placed between the chassis ground and the circuit ground. These ground connections can be made with a blade to keep open or jump with magnetic beads/high frequency capacitors.
If the board is not placed in a metal chassis or shield, solder resists should not be applied to the top and bottom chassis grounds of the board so they can act as discharge electrodes for ESD arcs.
An annular ground is placed around the circuit in the following manner: (1) In addition to the edge connector and the chassis ground, a circular path is placed around the entire periphery.
(2) Ensure that the annular width of all layers is greater than 2.5 mm.
(3) Connect the ring shape with a via hole every 13mm.
(4) Connect the ring ground to the common ground of the multilayer circuit.
(5) For double panels installed in metal chassis or shielding devices, the ring ground should be connected to the circuit publicly. The unshielded double-sided circuit should be connected annularly to the chassis ground, and no solder resist should be applied to the annular ground so that the annular discharge can act as a discharge rod for the ESD, and at least one position on the annular ground (all layers) A 0.5mm wide gap prevents the formation of a large loop. The distance between the signal wiring and the ring ground should not be less than 0.5mm. In the area that can be directly hit by ESD, a ground line should be placed near each signal line.
The I/O circuit should be as close as possible to the corresponding connector.
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