Due to the limitations of traditional technologies, the performance of video surveillance systems is difficult to improve. In order to solve this problem, based on the analysis of the consumption of various parts of the video surveillance system, the new technology of C2H (C-to-Hardware) is introduced to accelerate the hardware in the time-consuming part of the system. Improve the performance of the video surveillance system. The test data shows that after the application of C2H technology acceleration in the video surveillance system, the data read and write speed is increased by more than ten times, and the performance of the whole system is significantly improved.
This article refers to the address: http://
0 Preface
With the wide application of video surveillance systems, people put forward higher requirements for the real-time performance of surveillance systems. Especially in the high-speed data acquisition applications, traditional technologies are facing a severe test in processing speed. The current common solutions It is difficult to meet the increasing demands of users. To this end, Altera Corporation introduced C2H technology on April 7, 2006. The essence of this technology is to accelerate the C language directly by hardware through hardware mapping, and improve system performance.
In this paper, the C2H technology is applied to the data storage function of the video surveillance system, which effectively speeds up the reading and writing of data and greatly improves the performance of the system.
1 Introduction to C2H Technology
1.1 Characteristics of C2H
C2H is a technology that can directly customize hardware acceleration for ANSI C functions, and has been widely used by embedded and FPGA designers in just one year. The C2H compiler can analyze the type of memory interface that the program is to accelerate, generate hardware accelerator logic, and the appropriate Avalon (bus interconnect architecture) host and slave interfaces to match the memory latency. In this way, the processor's data calculation and memory access tasks are shared, enabling the processor to better handle other tasks. The data shows that the system performance accelerated by the Nios II C2H compiler is 10 to 45 times better than systems that do not use C2H acceleration, and the logic resources are only 0.7 to 2.0 times more expensive than the processor itself. The NiosII C2H Compiler is a plugin based on the Eclipse's NiosII Integrated Development Environment (IDE). At the same time, the C2H compiler has the ability to recognize parallel run events and run separate events in hardware simultaneously. Events that are not related to previous results will be executed as early as possible. Software calls are accelerated in a threaded manner - each accelerator runs completely in parallel, a true multitasking system (CPU, hardware accelerator).
1.2 C2H process
The use of C2H requires repeated debugging until the performance meets the design requirements. The specific process is as follows:
(1) Develop and debug C programs in Nios II;
(2) Analyze the C program to find the part that is most suitable for acceleration;
(3) Write the code segment that needs to be accelerated as a separate sub-function;
(4) Specify this function as a hardware accelerated function;
(5) Recompile the entire project in the Nios II IDE;
(6) Analyze the results of hardware acceleration and observe the C2H* estimation report;
2 Video surveillance system design
The EP2c35 FPGA in the Cyclone II family from Altera Corporation was chosen for the design. The Cyclone II family is a low-cost embedded processing solution with the ability to extend peripheral sets, memory, and I/O. At the same time, Altera provides the Nios II embedded processor for free. The NiosII soft core is a 32-bit RISC embedded processor with performance exceeding 200MIPS to meet current system design requirements. Altera offers a complete set of SOPC development tools for the Nios II soft core, making it easy to implement software from the underlying hardware to the upper layers.
2.1 Overall design of video surveillance system
The basic components of the video surveillance system designed in this paper are the real-time image acquisition camera, the video decoding chip AD7181B, the video D/A chip ADC7123, the VGA controller, the Flash, the SDRAM controller and the control core Nios IICPU. The entire system except the A/D and D/A uses a dedicated chip, and the rest is implemented on the FPGA. The hardware design block diagram of the video surveillance system is shown in Figure 1:
Figure 1 system hardware design block diagram
The functions of each module are described as follows: NiosII soft core CPU is a 32-bit RISC embedded processor, which is the hub of the whole system; SDRAM is a large-capacity data buffer storage area of ​​the system; Flash, storage system hardware and software system power-on Configuration data; video processing module, to achieve ITU656 decoding, deinterlacing, format conversion and other functions of the video stream.
2.2 Application of C2H in video surveillance system
Figure 1.2 below shows the processing of the video data stream in the system.
Figure 2 video data stream processing diagram
As can be seen from Figure 2 above, the data stream processing process is first converted to an 8-bit digital video signal by the analog-to-digital conversion of the video decoder chip AD7181B; and then decoded by the ITU-R656 decoder to make the video format YUV4:2 :2; Then deinterlace the video stream. In the deinterlacing process, the odd field data and the even field data need to be stored in two FIFOs (FIFO A and FIFO B), and then read in the order of ABABA... at twice the frequency to complete the video. Go to interlaced processing. Finally, after YUV to RGB time domain conversion, it can be displayed on the display under the control of the VGA controller. Since the video decoding A/D and the video D/A are performed by a dedicated chip, the speed is fast and does not have much influence on the speed of the system. After analysis and comparison, the bottleneck of system performance improvement is the data reading and writing in the data intermediate processing. This is the most time consuming part of the system because it involves reading and writing from memory. So the key to improving system performance is to reduce the time spent on data reading and writing. In this design, C2H technology is used for hardware acceleration of data reading and writing. The acceleration part of the procedure is as follows:
Among them, dest_ptr is the data destination address, source_ptr is the original data address, length is the number of bytes, and the length in the test is 1048576 bytes long.
The implementation process is described in Section 1.2 of the paper. First, after analyzing and comparing the time consumption, it is determined that the most time-consuming part is the data read and write part. Therefore, determine this link as the acceleration object, and write it as a separate sub-function, the above c2h_acceleraTIon function, then directly select the above function in the IDE, right click, select HardwareAcceleration, and finally regenerate the system and compile the entire project.
3 analysis of results
In order to compare the acceleration performance, a function similar to c2h_acceleration is defined in the system: software_acceleration, and then C2H acceleration is performed on the function c2h_acceleration. And compare the results with software_acceleration without C2H acceleration. The test function is defined, and some of the code is as follows:
After compiling and running, analyze the hardware acceleration results, observe the C2H* estimation report, and clearly see the performance improvement after C2H acceleration from the running results. The result of reading and writing 1048576 bytes of the function without C2H acceleration is shown in Figure 3 below. The result of the function accelerated by C2H is shown in Figure 4 below.
Figure 3: No C2H accelerated test results
Figure 4C2H accelerated test results
As can be seen from the results of Figure 3 and Figure 4, the software needs to read and write 1048576 bytes of data requires 86,520ms; after C2H hardware acceleration, the time consumption is reduced to 7470ms, and the speed is increased by up to 11 times.
4 Conclusion
This article describes a video surveillance system designed on the EP2c35 FPGA from Altera Corporation.
The author of this paper is innovative: the application of C2H technology in the video surveillance system accelerates the data read and write links, which improves the data read and write speed by 11 times and improves the performance of the entire system. The design method and implementation technology of this paper are suitable for application in video products with high requirements for real-time data processing, and have great practical value.
APM offers 3 Phase Ac Power Source system. It`s single 3-phase output Programmable Ac Power Supply which provides with high power density. With high speed DSP+CPLD control, high frequency PWM technology, active PFC design, It is able to provide not only stable DC/AC output power,but also 3-phase / 1-phase output.
The 3 Phase Ac Power Supply is featured with high power density, high reliability and high precision, meanwhile it possesses operation interface of touch screen and keys manually. It is able to analog output normal or abnormal power input for electrical device to meet test requirements, which is applicable to electric, lighting, aviation sectors, etc. It could be applied to enterprise`s production test as well.
Some features as below:
- 5.6" large touch color screen, possess complete functions and easy to operate.
- Support for USB data import/export and screen snap from front panel.
- AC+DC mixed or independent output mode for voltage DC offset simulation.
- Capable of setting voltage and current output restriction, support for constant current output mode.
- Capable of setting output slope of voltage and frequency.
- Capable of setting ON/OFF phase angle.
- With reverse current protection to avoid current flowing backward.
- Built-in power meter, which is capable of measuring 5 electrical parameters per phase, including voltage, current, power, etc.
- Support mA current measurement function.
Three Phase Ac Source System,Programmable 3 Phase Ac Power Supply,Ac Source System,Three Phase Source
APM Technologies (Dongguan) Co., Ltd , http://www.apmpowersupply.com