Transmission line theory explains that the source output is unaffected by impedance changes that may occur along the signal path between the input of a component. When an AC signal travels down a transmission line and encounters an impedance mismatch, part of the signal reflects back toward the source, while the rest continues to the receiver. The larger the impedance change, the more significant the reflection, which can lead to signal distortion and degradation in performance.
Impedance variations are influenced by several factors, including wire width, spacing between adjacent wires and components, and the distance from the reference plane. However, these changes are not always immediately visible on a printed circuit board (PCB). A practical approach is to review the PCB layout or system diagram to identify potential problem areas that may require further analysis through simulation. During this process, it's essential to trace the signal from the source to the receiver, check for any deviations from the guidelines listed in Table 1, and examine the points of failure discussed below.
**Table 1: Inspection Guidelines for Minimizing Reflections**
| Single-ended | Differential type |
|--------------|-------------------|
| Wire width must be constant | Differential wire spacing (coupling) and wire width must be constant |
| | |
| The spacing between wires and other devices and wires should be at least three times the wire width | |
| Constant reference plane must exist at the same distance throughout the length of the conductor | |
Not all situations require strict adherence to the guidelines in Table 1. However, certain areas are more prone to violations:
- **BGA traces**, especially for multiple I/O devices leading to internal rows or columns.
- **Vias**: Special attention is needed to ensure a consistent reference plane as signals pass through different PCB layers.
- **Online devices and connectors**: Their PCB packages often differ in size from the transmission line, causing impedance mismatches and reflections.
To maintain consistent impedance when routing to or from a BGA device, carefully manage trace width and the spacing of adjacent vias or pads. Figure 1 illustrates some common design considerations from the DS125DF1610 16-channel 12.5Gbps retimer data sheet (a 196-pin BGA device).
Starting from the top, the first rule combination in Figure 1 shows how to properly manage differential trace routing within BGA rows and columns. The second rule highlights a technique called "necking," where a narrower wire width may be used under the BGA. This is done symmetrically, with the neck length equal to the length of the two wires in the differential pair.
The third rule in Figure 1 demonstrates one method to ensure a constant reference plane for signal vias. Here, four ground vias are placed near the signal vias, helping the signal maintain a stable ground reference across different PCB layers. While four ground vias are common, two may be sufficient in many cases—always verify through simulation.
It’s also crucial to manage the impedance of in-line device and connector package pads. During inspection, check for gaps or voids in the reference plane around the pads. Even small discrepancies can cause issues if the pad dimensions significantly differ from the transmission line.
Figure 2 shows a signal trace running to an inline device, such as a pair of AC-coupling capacitors. Figure 3 displays the ground plane beneath the conductor, highlighting a notch below the device pad that helps match the impedance to the transmission line, reducing reflections. Figure 4 shows the top etch and ground plane configuration.
Finally, simulations are essential to validate your PCB layout and ensure minimal signal reflections. By following good design practices and using the guidelines provided, you can reduce simulation time and improve overall performance. Always test thoroughly and keep these principles in mind during the design process.
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