Under the trend of increasing safety in the automotive industry, vehicles need to integrate more and more peripheral photography sensors and intelligent image processing technologies in order to achieve advanced driver assistance systems (ADAS), such as lane departure warning, collision avoidance, blind spot monitoring, Advanced reversing photography and surrounding environment observation system with object recognition function, etc. The common goal of manufacturers to create a completely safe driving environment is driving this trend. For example, Volvo's "Zero-by-2020" goal is to hope that people who ride the new Volvo car by 2020 will no longer die or even be injured in a car accident.
The challenge for these systems is the need to build a platform that can maintain the processing performance required by these computationally intensive applications, consumes less power to avoid heat dissipation, can provide cost-effective solutions that integrators are willing to adopt, and the system The size should be small so that the "brain" of the system and the image sensor are co-located and assembled into the smart camera (if required). The image processing coexisting on the sensor can constitute a system solution. In this system, the same smart photography platform can be applied to different positions of the vehicle, such as the rear bumper-an enhanced reversing camera with object / body detection ; Mirrors-for blind spot monitoring; behind the rear-view mirror-for forward collision and lane departure warning; and other peripheral cameras-for the surrounding environment observation. In addition, this distributed intelligent photography model does not burden the car's center console with additional processing requirements.
Figure 1: Advanced driver assistance system.
The market report pointed out that in the next few years, ADAS will not only be widely used in high-end cars, but also in more common low-end cars. In addition to requiring each application to provide stronger computing performance, there are also demands for more ADAS applications combined on the same hardware platform. But this also raises a doubt-is the current DSP and FPGA solution enough?
One of the biggest bottlenecks in the DSP algorithm execution scheme is the increasingly heavy external memory to keep up with the speed of read and write access. Traditional DSPs provide limited parallel execution capabilities. In order to meet processing requirements, they usually require working at higher and higher frequencies. As the frequency continues to rise, the DSP will consume more power, which in turn generates more heat and needs to be dissipated. Although the parallel execution capability of FPGA is stronger than DSP, it is more difficult to program, and often requires RISC processor for post-processing of data. FPGA also has a lot of power consumption, and the system size is large, in short, it is a higher cost solution.
The future of image recognition: multi-core parallel processing
The multi-core parallel processing performance performed by the CogniVue image recognition processor (ICP) has surpassed DSP and FPGA in many aspects. Within the unit area and unit milliwatt power, ICP can provide better cost performance.
The CogniVue APEX architecture integrates an industry standard RISC core for managing algorithm execution and a highly parallel single instruction multiple data (SIMD) array processing engine (APU) that can be used to perform low-level, computationally intensive parallel operations inherent in image processing and analysis algorithms . In addition to RISC and APU, this architecture also has a newly designed streaming DMA to ensure efficient data movement; and a sequencer designed for automatic and efficient sorting operations to ensure maximum efficiency. The second RISC core operates independently outside APEX and is used to process system-level resident programs.
APU internally prepares local dedicated memory for each computing unit. The image data is taken from the external memory, and then flows into the APU memory. Before the data flows out and is stored in the system memory, all processing work is completed in the APU memory. Since the APU memory and the APU unit are located at the same place, the number of external memory accesses can be greatly reduced, and high computing performance can be maintained without increasing the frequency. The APEX processing core is also separate from the rest of the ICP, which means that the operating frequency of the APEX core is independent of the rest of the SoC, allowing the rest of the component to operate at a lower frequency, thereby saving power. By stacking external memory inside the package, this solution can achieve a smaller system size and save board space.
Due to the use of parallel processor cores and unique software paradigms based on streaming programming, CogniVue ICP can schedule complex vector operations and execute program code with minimal data movement. These processors implement automatic pipelined operation of algorithm primitives whenever possible, and capture this complexity through a comprehensive API, thereby hiding the complexity of system load balancing and eliminating the multi-core synchronization faced by developers problem.
The highly parallel mechanism coupled with the high ALU bandwidth architecture demonstrates a viable platform that provides sufficient spare functions and processing power to execute multiple applications in parallel on the same hardware. The flexible development platform and SDK enable users to flexibly program APEX and build highly competitive differentiated applications. The reason why this multi-core parallel platform can be favored by developers is not only because it can provide advanced performance, power consumption and size characteristics, but also to ensure that the program code in the future ICP is reused, thereby ensuring the minimum development work and time.
Figure 2: Parallel architecture of programmable design.
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