High-definition media consumption is experiencing double growth. One is the increase in the number of consumers, and the other is the transition to more high-definition content. The growth is driven by the growing popularity and speed of Internet access services and the explosive growth of mobile devices (mobile phones, tablets, wearables, etc.). Therefore, many wearable devices today can handle the consumption of high-definition media.
Even with the most conservative estimates, by 2020, demand for Internet of Things (IoT) and wearables will triple. This means there will be 50 billion pieces of equipment worldwide. This will create a need for a new generation of display drivers and frame buffers, a memory that is different from the memory used in conventional displays. While embedded RAM can meet the needs of first-generation wearable devices, today's HD and large wearable displays require much larger frame buffer memory. These requirements are different from traditional PC and TV displays because they are battery powered and energy efficiency is the primary design constraint. Most of the latest wearable devices will be extremely space efficient and energy efficient, so that they will be able to work continuously for days or even weeks after being fully charged, while still performing a variety of complex operations. That's why we need a new generation of displays for their drives.
In order to understand the frame buffer requirements of wearable devices, let us first study the architecture of the graphics system. Each graphics system consists of three components: hardware, a graphics library, and an application that uses it.
Graphics libraries and applications are controlled by software, while hardware is controlled by a frame buffer, which is a continuous high-throughput memory. Each of the memory cells in the frame buffer corresponds to one pixel on the screen. The pixel intensity is determined by its voltage.
The resolution of the display is determined by the following factors:
Number of scan lines
Number of pixels per line
Number of bits per pixel
Take a 1024x768 24-bit image as an example, which is the most common screen resolution for PCs.
1024 X 768 X 24 = 18.9Mb
This is the minimum amount of space required for the frame buffer to support such a display. However, if it is a dynamic display with video capabilities, only one memory of this size is not enough. This puts a throughput requirement on the frame buffer.
For a video of 30 frames per second (fps) at the above resolution, the maximum throughput is: 18.9 x 30 = 566 Mbps.
As described above, each of the memory cells in the frame buffer corresponds to one pixel on the screen. For an n-bit color display, each of the n bits is a single bit plane (eg, a 24-bit color has 24 bit planes). N memory cells will store the state of each pixel, and binary values ​​from each n-bit plane are loaded into corresponding locations in memory. The final binary number is interpreted as an intensity value between 0 and 2n – 1 and then converted to an analog voltage between 0 and the maximum voltage by a digital-to-analog converter to achieve 2n intensities.
Two factors determine the type of frame buffer used by the display: capacity and throughput. Increasing the resolution of the image requires more memory, and increasing the fps of the video requires higher throughput. There are two ways to satisfy this requirement: increase the capacity and throughput of the frame buffer, or reduce throughput by increasing the capacity of the frame buffer (for example, doubling the former and halving the latter). By increasing the frame buffer's capacity (usually integrating multiple frame buffers in a single chip), we are able to reduce throughput because the input-output cycles that the chip must experience are reduced. For example, after doubling the capacity, two frames can be stored in one buffer at the same time, which means that the number of times the buffer is called/referenced is reduced by half in a given time, thus achieving lower throughput. . Therefore, memory is divided into two categories: high density and high throughput. This aspect will be discussed later in this article.
After carefully looking at the specifications of Nvidia and AMD's latest generation of computer graphics processing units (GPUs), we found that the memory capacity has increased dramatically, usually to a few gigabytes. This is because most modern GPUs are designed for gaming and HD rendering applications, and there are a number of additional features that take up memory space: MSAA (using the sampling frequency to double the buffer capacity), prefetch, shadow buffer, Delayed rendering and effects. Even the functions we take for granted, such as window scrolling, take up extra buffer space. Most game buffers use triple buffering (three buffers per frame) and HDR (normal HDR depth is 64 bits instead of 24 bits). Many of these high-end GPUs also support multiple HD displays, which means a dedicated buffer is built into each display.
However, due to their small display size, most wearable and portable devices do not require these features. The ideal method is to use the MCU's embedded memory resources as a frame buffer. It will have the highest throughput and is the easiest to implement. However, for a new generation of displays in wearable devices, most MCUs do not have enough memory. In addition, increasing program complexity requires larger embedded memory to be used as a Level 1 cache for the MCU. For most contemporary wearable devices, the resolution of the display is QVGA (Quarter Video Graphics Array), and for these displays, the following specifications will be sufficient: 24 bit | 480*360 | 30fps. For wearable device displays, they mean up to 300 pixels per inch (ppi). The memory requirement for this type of display is 4Mb of memory with a throughput of 120 Mbps. However, future devices will be equipped with much higher resolution displays, over 400 ppi, which is comparable to many of the latest generations of mobile phones. For displays of the same size, the increasing ppi means that the frame buffer capacity is correspondingly increased. As mentioned above, there are two ways to implement a frame buffer of this capacity: a 4Mb buffer with a throughput of about 120 Mbps or a 16Mb buffer with a throughput of about 30 Mbps. In both approaches, small-capacity buffers have many benefits—smaller size (chip or CSP), lower power consumption, lower cost, and more choices (with increasing capacity density, vendors and product categories) Will be less and less). For wearable devices, size, power consumption, and cost are the most important determinants of all device components.
The most widely used framebuffer memory is dynamic RAM (DRAM), although the most common memory of the most common is static RAM (SRAM). DRAM consumes more power than SRAM, and throughput is lower than the latter. Although SRAM's performance is extremely high, it is ideal for the latest generation of portable devices, but most battery-backed devices do not use them because SRAM has a small variety of products, only low-density products, up to 128Mb. The structure of the SRAM memory cell is complicated, consisting of six transistors, and the DRAM memory cell is composed of one transistor + one capacitor. This is why SRAM is limited in increasing density, and this has proven to be its biggest limitation. Although SRAM is not applied to traditional consumer electronic devices (PCs, TVs, mobile phones, etc.) due to this limitation, SRAM is not a bad thing for wearable devices, considering the small frame buffer memory required for wearable devices. In addition, in these devices, higher performance (higher throughput is equivalent to lower power consumption) is also a big advantage of SRAM.
With the return to high-performance, especially low-power requirements, the type of memory that has been seen as extinct - SRAM - seems to be reviving. You can read this article to learn about SRAM in next-generation wearable and IoT devices. The article describes the use of SRAM beyond framebuffer: from memory expansion to data logging.
Many leading SRAM vendors have introduced a range of innovative technologies to meet the needs of wearable systems: from higher reliability to new packaging formats. In the field of high-definition video recording and processing, Cypress also has a resounding HD frame buffer series. For more details on the configuration of frame buffer memory and the HD frame buffer family, please refer to the following application note: Using High Density Programmable FIFOs in Video and Imaging Applications.
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