introduction
In recent years, network technology has developed rapidly, and Ethernet has dominated the market. This design uses Atan's switching chip AT89818 as the core chip, and AT89C52 as the system setting and configuration chip. The switch provides good flexibility and ease of handling for the upgrade of Fast Ethernet. It provides 16 multi-channel 10M / 100Mbps RJ-45 Ethernet ports. The switch will automatically detect the speed of the connected device, allowing 10Mbps and 100Mbps devices to be used on the same switch without replacing the original network facilities.
1 System function 
The system complies with the IEEE 802.3-802.3u standard, and the interface is 16-port 10 / 100Mbps multi-channel switching (using shielded RJ-45 connectors). The system has an address table that can store up to 8K MAC address entries, and has the feature of store-and-forward switching, so that it can automatically learn and store the addresses in the MAC address table; it has a dynamic O / I buffer of shared memory, thus ensuring Fast and error-free packet storage and packet forwarding; adopts plug-and-play configuration automatic learning mode, supports half-duplex and full-duplex modes, and has another MDI port for cascading. The main technical indicators are
Maximum forwarding rate:
14 880pps / 10BASE-T; 148 800pps / 100BASE-TX.
Maximum filtration rate:
14 880pps / 10BASE-T; 148 800pps / 100BASE-TX.
2 System configuration
The switch system uses AT89818 as the core switching chip; the MCU uses AT89C52, which is used for control and system settings, and has been in communication with the computer; the EEPROM uses AT93C46, which is used to store the initialization data required when the switch starts; W25P243A; PHY0 and PHY1 use 8-port DSP 10/100 PHY; JACK0 and JACK1 are RJ-45 connectors. The system structure is shown in Figure 1.
2.1 AT89818
AT89818 is the center of the entire hardware system and the core switching chip. AT89818 can have up to 18 10M / 100Mbps multiplex switch interfaces, one or several of which can be bundled, the chip has an address table of 8192 MAC address entries, and VLAN can also be set through EEPROM.
â—‡ Support store and forward function;
â—‡ Each VLAN packet can have 1522B cache;
â—‡ Support aging function and 802.3x flow control;
â—‡ Seamlessly connect 64K & TImes; 64 bit or 128K & TImes; 64 bit SRAM;
â—‡ Broadcast storm control is possible;
â—‡ Two bundling groups based on MAC address, each group can have 2 ~ 6 ports;
â—‡ Support port-based VLAN technology configured through EEPROM;
â—‡ The speed, half-duplex or full-duplex mode, bundling mode, VLAN setting, etc. of each port can be configured through EEPROM.
figure 2
2.2 MCU (AT89C52)
AT89C52 is used as the chip for system setting and control. The MCU can communicate with the computer through the serial port, and control and set the management of the switch through the computer; at the same time, it and AT89818 alternately obtain control of the EEPROM. When the switching chip hands over control of the EEPROM to the MCU, the MCU reads, writes, and modifies the EEPROM. After the modification is completed, the MCU can hand over the control rights to the switching chip, and the switching chip then reads the configuration data from the EEPROM again.
2.3 Other devices
(1) EEPROM
Using the three-wire CMOS device AT93C46, the data format of the EEPROM can be selected as 64 & TImes; 16 or 128 × 8 by setting the ORG pin high or low. Connected with MCU through CS, SK, DI, DO, MCU can read and write data stored in EEPROM.
(2) PHY
Using M88E3080. It is an 8-port 10M / 100Mbps Fast Ethernet physical layer transceiver device with higher signal-to-noise ratio and lower power consumption. It is a product of Marvell Semiconductor Inc.
(3) SRAM
Using W25P243A. It is a 64K × 64 PIPLINED CMOS high-speed static RAM, which is a product of Winbond Electronics.
image 3
3 Design of the key circuit of the system
3.1 Design of the system clock
Since the clocks of both PHY chips are 50MHz, and the clocks of SRAM and AT89818 are both 75MHz, they are already designed for high-speed digital circuits, so signal integrity must be considered when designing.
As shown in Fig. 2, through the buffer 74LVT244 can increase the driving capacity of the clock, generate 2 in-phase, extremely low delay and consistent clock output to the 2 PHY, can ensure the integrity of the signal.
In addition, PCB design should also keep high-speed signal traces as short as possible to ensure the integrity of the system signal design. 
3.2 System design of control between MCU and EEPROM, AT89818
Figure 3 shows the connection between MCU and AT93C46. MCU can read and write to AT93C46 through EDO, EDI, ESK, ECS; meanwhile, EDO, EDI, ESK, ECS are also connected to DO, DI, SK, CS of AT89818, respectively. AT89818 and MCU exchange control of EEPROM through E2TR. When E2TR is low, AT89818 reads configuration data from EEPROM through DO, DI, SD, CS; when E2TR is high, the four signal lines of AT89818 are in high impedance Status, the control of the EEPROM is handed over to the MCU, and the MCU can modify the data in the EEPROM at this time. Within 30ms after the system restarts, E2TR must remain low.
3.3 AT89818 connected with PHY and SRAM
The connection between AT89818 and M88E3080 and SRAM is shown in Figure 4. MDC is the 1MHz clock output by the switch chip and is used to drive the PHY chip. In order to increase the driving capacity, consider using the buffer first. MDIO manages the DATA line used by the PHY chip for the switching chip.
4 Application prospects
This switch is a network device with fast Ethernet switching, high performance, and low power consumption. In recent years, the network has developed rapidly, and many communities are considering fiber-to-the-home when constructing. This equipment can fully meet the needs of the majority of users with many advantages such as economy, practicality and high efficiency.
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